Magnetoelectronic devices incorporate a ferromagnetic material as part of a digital electronic device and use the bistability of magnetic hysteresis as a basis for nonvolatile storage. High performance integrated magnetic random access memory (MRAM) chips have been commercially available since 2006 and are highly competitive with semiconductor static random access memory (SRAM). The dominant magnetoelectronic device that's used as the storage cell in MRAM is the magnetic tunnel junction (MTJ). The MTJ in a storage cell has a pinned ferromagnetic layer (FP) and a free ferromagnetic layer (FF) that are separated by a tunnel barrier (FIGS. 1A-B). The free layer has a uniaxial anisotropy axis (along the x-axis in FIG. 1A) such that the magnetization has two stable states, parallel or antiparallel with the magnetization orientation of FP. Commercial MRAM cells face two roadblocks that stand in the way of achieving higher bit-count chips and broader market penetration.
The first issue involves the write process. This process uses integrated “write wires.” A two dimensional array of cells is overlaid with a two dimensional array of rows and columns of write wires. Each write wire is inductively coupled to each cell in the row or column. A current pulse applied to any wire has a local magnetic field associated with the current. To write a cell at location (j, m), a “half-select” process is used. The current pulse amplitude IW is chosen to be sufficiently small that the fringe field does not disturb the orientation of FP of any cell along the row or column. However, the sum of the fringe fields of pulses with amplitude IW applied to a row wire and a column wire will be sufficiently large to flip the magnetization state of FP at the intersection of the two wires, for example the cell at (j, m). This write process is called “Oersted” writing. The current pulse amplitudes are relatively large and the power dissipation is high. Furthermore, this write process is not scalable: when the cell size is reduced, the write power is not reduced.
An alternative to “Oersted” writing is called the “Spin Torque Transfer” (STT) write process. In this technique, spin polarized electric current from a reference ferromagnetic layer are driven into FP. Spin angular momentum from this “write” current is transferred to the conduction electrons in FP and, for sufficient current amplitude and pulse durations of order 1 nsec, the magnetization orientation of FP is set. This technique requires an architecture with a “select” transistor for each cell. However, the STT write process uses less current than the Oersted process. Of more importance, STT writing is scalable: the write current decreases as the cell size decreases.
Research on the STT process applied to MTJ cells is advanced, but the technique has fallibilities that have limited commercialization. The pinned layer can be used as the reference layer, but driving the STT current across the tunnel barrier creates heat. The application of repeated write pulses deteriorates the barrier and leaves it susceptible to dielectric breakdown. Referring now to FIG. 1B, the write current Iwrite is driven across tunnel barrier. A high write voltage dissipates high power which eventually degrades the tunnel barrier and destroys the MTJ.
The second issue involves reading out the datum value (cell readout). The product of MTJ area and resistance, RA, is constant for a given materials stack. As the area A decreases, the device resistance increases as the square of the feature size f. The best materials stacks are characterized by RA values of roughly 500Ω-μm2. For a commercially competitive prototype with f=50 nm, the resistance is R=0.2 MΩ. The MTJ readout voltages (˜50 mV) are supplied to “sense amplifiers” matched to 50Ω impedance circuits. The 0.2 MΩ output impedance provides a large impedance mismatch that dramatically diminishes the readout performance.